User guide

11.1.4.2 NMI Status and Control Register
Figure 11–14 shows the NMI status and control register.
Figure 11–14 NMI Status and Control Register
31 08 07 06 05 04 03 02 01 00
ML013458
HALT Status
Ignore on read
Don't Care
HALT Enable
SERR Enable
Ignore on read
SERR # Status
Table 11–4 contains more details about the settings in the NMI status and control
register.
Table 11–4 NMI Status and Control Register Bits
Field Name Type Description
<7> SERR# Status RO Bit <7> is set if a system SERR has occurred.
The interrupt in response to this event is enabled
by clearing bit <2> of this register to a 0. Bit <7>
can be cleared only by setting the SERR enable
bit (bit <2>) to a 1 and then back to a 0. Always
write this bit as a 0.
<6> HALT Status RO Bit <6> is set when either the watchdog timer
expires (and is enabled) or the HALT switch is
toggled. This interrupt is enabled by clearing bit
<3> of this register to 0. Bit <6> should always
be written as a 0. To clear this status bit, set bit
<3>, and then clear it again to reenable this NMI
event reporting.
<5:4> - R/W Ignore on read. Writes must be 0.
(continued on next page)
11–12 System Interrupts