User guide

Figure 11–11 VIC Error Group ICR
31 08 07 06 05 04 03 02 00
ML013310
ACFAIL* Interrupt Mask
Write Post Fail Interrupt Mask
Don't Care
Arb. Timeout Interrupt Mask
SYSFAIL* Interrupt Mask
SYSFAIL* Asserted
IPL for this group of Interrupts
VME_IF_BASE + 48 :
VIC_EGICR
Finally, a local (on-board) interrupt is generated by the VIC64 chip when the
VME interface detects a VMEbus IACK cycle to itself. The VIC64 chip can
notify the CPU when the VME interface, as a VMEbus interrupter, has its
interrupt acknowledged. Once again there is an associated ICR, VIC_VIICR
(see Figure 11–12), to set the IPL and allow the condition to be disabled from
generating its local interrupt.
Figure 11–12 VMEbus Interrupter ICR
31 08 07 06 03 02 01 00
ML013311
Disable
Don't Care
Encoded Priority 1-7
VME_IF_BASE + 00 :
VIC_IICR
There is a single interrupt vector base register for the error-group DMA and
‘‘interrupter-sees-IACK’’ interrupts (see Figure 11–13). In a similar way to
the device interrupts outlined above, the vector root (vector bits <7:3>) is user
programmable while the least significant 3 bits are different for each condition.
In this way, there is a unique interrupt vector for each of these error/status
events.
11–10 System Interrupts