User guide

Figure 11–9 VME IRQ* ICRs
31 08 07 06 03 02 01 00
ML013305
Disable
Don't Care
Encoded Priority 1-7
Table 11–3 VME IRQ ICR Priority Assignments
Address Register Line
:VME_IF_BASE+04 VIC_ICR1 1RQ1
:VME_IF_BASE+08 VIC_ICR2 IRQ2
:VME_IF_BASE+0C VIC_ICR3 IRQ3
:VME_IF_BASE+10 VIC_ICR4 IRQ4
:VME_IF_BASE+14 VIC_ICR5 IRQ5
:VME_IF_BASE+18 VIC_ICR6 IRQ6
:VME_IF_BASE+1C VIC_ICR7 IRQ7
Within the system, VMEbus interrupts compete (based on IPL and ranking) with
other system interrupts. If, during a local bus IACK, a VMEbus source is the
IRQ winner, the VIC64 chip initiates a VMEbus IACK cycle to retrieve the bus
interrupter’s vector. The VMEbus vector response is passed back to the DECchip
21064A in response to the system read of the VIP_IRR register.
It is assumed that the VMEbus interrupter releases the IRQ line either on seeing
the VME IACK or because of the action (register write, and so forth) of the
interrupt service routines (ISRs).
11.1.3.3 Status/Error Interrupts
Internal to the VIC itself are a number of conditions and errors that can be
reported by an interrupt request.
The conditions that can be enabled to cause system interrupts are:
• VMEbus SYSFAIL* assertion
• VMEbus ACFAIL* assertion
• VMEbus arbitration timeout
• VIC write post failure
11–8 System Interrupts