User guide

11.1.2.1 Basic Operation
The VIC64 chip handles 19 interrupt sources. Each of these can be individually
programmed to any of the seven IPLs in the controller’s interrupt control registers
(ICRs). The generic form of the ICR is shown in Figure 11–6.
Figure 11–6 Generic ICR
31 08 07 06 03 02 01 00
ML013305
Disable
Don't Care
Encoded Priority 1-7
A fixed relative ranking for requests is defined. This ranking is shown in
Table 11–2, and is used to decide which interrupt is reported if many interrupts
are pending.
When a VME interrupt is identified, the CPU initiates a read of the VMEbus
interface processor interrupt reason register (VIP_IRR), which is read to retrieve
the vector from the VIC/DC7407. The read of the VIP_IRR generates a local
bus IACK cycle at the pins of the VIC64 chip. When the VIC64 chip detects
the IACK cycle, it responds with the vector and IPL of the winning interrupter.
The controller determines the highest ranking active interrupt request to be the
winning interrupt. The vector returned from the VIC64 chip and the current IPL
are concatenated and returned to the processor.
System Interrupts 11–5