User guide

Figure 11–1 Block Diagram of the Interrupt Logic
VIC_IPL2
VIC_IPL1
VIC_IPL0
VME Reset
Interval Timer IRQ
Periodic RT Timer
Timer #1 IRQ
1 ms Heartbeat Timer
PMC0 IRQA
PMC1 IRQA
PMC0 IRQB
PMC1 IRQB
PMC0 IRQC
PMC1 IRQC
PMC0 IRQD
PMC1 IRQD
SCSI IRQ
Ethernet IRQ
SIO IRQ
(Super I/O) IRQ <7:3>
(Mouse) IRQ12
(Keyboard) KB_IRQ
PCISERR
HALT
SIO
NMI
VME Connectors
VME_IRQ1
through
VME_IRQ7
Interrupt Priority
Lines VIC64
DC7407 (VIP)
XILINX
Interrupt
Controller
CPU_IRQ3



CPU_IRQ2



CPU_IRQ1



CPU_IRQ0




CPU_IRQ4

CPU_IRQ5
CPU
21064A
PCI
Host
Bridge
VIPSTATUS IRQ
VIPERROR IRQ
ML013320
11.1.1 Xilinx Interrupt Controller
The cpu_irq[3:0] are generated by four interrupt/mask registers contained in a
Xilinx FPGA, as shown in Figures 11–2 through 11–5.
• cpu_irq3 is controlled by bits [3:0] in interrupt/mask register 1
• cpu_irq2 is controlled by bits [5:4] in interrupt/mask register 1
• cpu_irq1 is controlled by bits [2:0] in interrupt/mask register 2
• cpu_irq0 is controlled by bits [7:0] in interrupt/mask register 3 and bits [1:0]
in the interrupt/mask register 4
11–2 System Interrupts