User guide

11
System Interrupts
11.1 System Interrupts
Figure 11–1 shows a schematic overview of the interrupt structure in the Digital
Alpha VME 4 system. Most interrupts are routed through the VIC64 chip, the
Digital Alpha VME 4 interrupt controller, and the SIO chip.
The 21064A receives six interrupts (CPU_IRQ[5:0]). The six interrupts are
identical, asynchronous, level sensitive, and can be masked by PALcode
individually.
Table 11–1 lists the CPU interrupt assignments during normal operation.
Figure 11–1 shows a block diagram of the interrupt logic.
Table 11–1 Table of CPU Interrupt Assignments
CPU Interrupt
Interrupt
Source Description
cpu_irq0 Interrupt
registers 3 &
4
PCI device interrupts from SCSI, Ethernet,
multifunction PMC options, SIO chip, and VME
interrupts [3:1]
cpu_irq1 Interrupt
register 2
PCI device INTA from PMC options and VME
interrupts [6:4]
cpu_irq2 Interrupt
register 1
VIP location monitor status and the 1 ms heartbeat
timer
cpu_irq3 Interrupt
register 1
Interval timer, VMEbus reset, and VMEbus
interrupt 7, VIP/VIC error and status, and periodic
real-time timer
cpu_irq4 82378 SIO chip nonmaskable interrupt
cpu_irq5 DC7277 APECS PCI bridge
System Interrupts 11–1