User guide

10.7 VME Subsystem Restrictions (as of 03-Jun-94)
This section describes limitations on the use of the VME subsystem due to
outstanding hardware constraints. The intention is that these will be eliminated
as new revision hardware components become available. This section will be
updated as restrictions change. Please contact your field application engineer for
the latest status on these constraints.
10.7.1 Collision of VIC64 Master Write Posting with Master Block
Transfers
Write Posting in the VIC64 should not be enabled. Collisions of outbound cycles,
cycles posted in the VIC64, and incoming VME slave cycles may cause a deadlock
condition that is not detected by the VIC64.
If the VIC64 Local Bus timer is enabled, this deadlock condition will generate
a Local Bus timeout error. If the VIC64 Local Bus timer is not enabled, this
deadlock condition will persist, causing the Local Bus and possibly the VMEbus
to hang.
A collision of the following three cycles will cause a bus timeout error:
• Posted master Write in the VIC64/CY964
• Alpha VME CPU is being accessed as a VME slave
• Master block transfer is being initiated by a ‘‘pseudo write’’ to the VIC64 over
the Local bus
10.7.2 VIC64 Errata: A16 Master Cycles During Interleave
The Cypress VIC64-00 Design Considerations document (dated 22 February 1994)
lists the following errata:
‘‘ A16 master cycles during an interleave period with dual path enabled will cause
BERR* and LBERR* to be asserted. ’’
Followup conversations with Cypress (and testing) have determined that a
further statement must be added. Apparently, the problem only occurs if the
DMA enable bit is set (BTCR<6>). The DMA drivers used with the Alpha VME
systems always clear this bit immediately after the ‘‘pseudo-write’’ to avoid any
PIO being taken as another ‘‘pseudo-write.’’ Therefore, BTCR<6> is always clear
by the time an A16 access could get through in an interleave gap.
While this is not a problem for customers using driver software supplied by
Digital, anyone writing their own interface to the VIC64s DMA engine must use
the same sequence to ensure this problem is not encountered.
10–40 VME Interface