User guide

Bits 3-0 Interleave period. Recommend a value of 0xF.
Bit 4 Data direction bit: 0=write, 1=read.
Bit 5 MOVEM enable. Recommend this be clear.
Bit 6 BLT with local DMA enable.
Bit 7 Module based DMA transfer enable.
BTLR1-0 Registers for block transfer length for local DMA block mode transfers.
SRR System reset register.
10.6 Summary of VME Interface Registers
Table 10–16 VME_IF_BASE +
00 VIC_IICR VMEbus interrupter interrupt control register
04-1C VIC_ICPR1-7 VMEbus interrupt control registers 1-7
20 VIC_DMASICR DMA status register
24-3C VIC_LICR1-7 Local interrupt status register
40 VIC_ICGISR ICGS interrupt control register
44 VIC_ICMSICR ICMS interrupt control register
48 VIC_EGICR Error group interrupt control register
4C VIC_ICGSIVBR ICGS vector base register
50 VIC_ICMSVBR ICMS vector base register
54 VIC_LIVBR Local interrupt vector base register
58 VIC_EGIVBR Error group interrupt vector base register
5C VIC_ICSR Interprocessor communications switch register
60-70 VIC_ICR0-4 Interprocessor communications registers 0-4
74 VIC_ICR5 Interprocessor communications register 5
78 VIC_ICR6 Interprocessor communications register 6
7C VIC_ICR7 Interprocessor communications register 7
80 VIC_VIRSR VMEbus interrupt request/status register
84-9C VIC_VIVBR1-7 VMEbus interrupt vector base registers 1-7
A0 VIC_TTR Transfer timeout register
A4 VIC_LBTR Local bus timing register
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VME Interface 10–37