User guide

Figure 10–14 VIC Interrupt Request/Status Register
31 08 07 06 05 04 03 02 01 00
ML013345
IRQ7
IRQ6
Don't Care
VME_IF_BASE + 80 :
IRQ5
IRQ4
IRQ3
IRQ2
IRQ1
Enable(1)/Disable(0)
VIC_VIRSR
Table 10–10 VIC Interrupt Request/Status Register
Field Name Description
<0> Controls whether the IRQs are reset or asserted. When <0>
= 1, setting any of the bits <7:1> asserts the corresponding
IRQ. When <0> = 0, setting any of the bits <7:1> clears the
corresponding IRQ. For example, when <0> is set, setting <4>
asserts IRQ4.
<1> IRQ1
<2> IRQ2
<3> IRQ3
<4> IRQ4
<5> IRQ5
<6> IRQ6
<7> IRQ7
A Digital Alpha VME 4 system uses the Release-On-Acknowledge method for
removal of its interrupt requests. As an alternative, the interrupt requests can be
deasserted by writing to the same VMEbus interrupt request/status register that
is used to assert the IRQ* lines. When a Digital Alpha VME 4 system detects an
IACK cycle on the VMEbus for one of its interrupt requests, it responds with a
vector that is programmable in the VMEbus interrupt vector base registers (see
Figure 10–15), starting at PCI memory address VIF_ABR+0x84.
10–24 VME Interface