User guide

Table 10–8 (Cont.) VIC Release Control Register

Field Name Description

<7:6> Release protocol Speciﬁes the release mode, according to the following values:

00 Release-on request (ROR)

the Digital Alpha VME 4 system keeps ownership until

another device requests the bus.

01 Release-when-done (RWD)

the Digital Alpha VME 4 system releases the bus

immediately after completion of the cycles for which

it requested ownership.

10 Release-on-clear (ROC)

the Digital Alpha VME 4 system retains ownership of the

bus after completion of the cycles for which it requested

ownership, until the system controller asserts the Bus

Clear signal.

11 Capture and hold (BCAP)

the Digital Alpha VME 4 system claims ownership of the

VMEbus for as long as the BCAP mode is selected. The

VMEbus is only released when the Digital Alpha VME 4

system is reprogrammed to another release mode.

10.3.2 System Clock Output

As the system controller, the Digital Alpha VME 4 system drives the system clock

(SYSCLK) for the VMEbus. The clock is a ﬁxed 16 MHz clock with a nominal

50% (+/- 10%) duty cycle. This 16 MHz timing has no ﬁxed phase relationship

with other bus timings.

10.3.3 Timeout Timers

10.3.3.1 Arbitration Timers

By default, the Digital Alpha VME 4 system operates as an arbitration watchdog

when conﬁgured as VMEbus system controller. After issuing a VMEbus grant

to the winning requester, the VME interface monitors the bus and, if it does

not detect activity (BBSY* asserting) within 8 µs, it asserts the BBSY* signal

to terminate the bus ownership and to allow rearbitration of the VMEbus.

This arbitration timeout cannot be disabled. However, the condition can be

used to generate a local interrupt to the processor. Control of this interrupt is

through the VIC error group interrupt control register (VIC_EGICR). For more

information, see Chapter 11.

VME Interface 10–21