User guide

Because the global switches are meant to be issued to several modules, the slave

targets of a global switch access do not acknowledge the cycle, but rather the

master driving the write data transfer acknowledgements (DTACKs) the cycle

itself (the VIF_ABR should be set to generate a self-access by the global-switch

write).

A write to an even address clears the selected switch and a write to an odd

address sets the switch.

If global-switch interrupts are enabled in the VIC64 interprocessor communi-

cation global switch interface conﬁguration register (ICGSICR), an interrupt

is generated to the local processor by way of the system interrupt controller.

The vector for the interrupt is generated from the VIC64 interprocessor

communication global switch interface vector base register (ICGSVBR).

Bits <4:0> in the ﬁnal register are set when there is a write access to the

corresponding interprocessor communication group processor register (ICGPR).

See the VIC64 speciﬁcation for more complete details.

10.2.3.3 Interprocessor Communication Module Switches

The Interprocessor Communication Module Switches (ICMSs) are software-

writable switches that can be set over the VMEbus to interrupt a processor. The

module switches, however, are meant to be issued to a speciﬁc module.

Because the module switches are meant for a speciﬁc module, the cycle is just like

a normal write on the bus (unlike for the global switch interface).

If interprocessor communication module-switch interrupts are enabled in the

VIC64 interprocessor communication module switch interface conﬁguration

generated from the VIC64 interprocessor communication module switch vector

base register (ICMSVBR).

Table 10–6 Interprocessor Communication Register Map Through VIF_ABR

<byte 1>+ Register

Interprocessor communication registers (ICR)

01 8-bit general-purpose register 0 R/W

03 8-bit general-purpose register 1 R/W

05 8-bit general-purpose register 2 R/W

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VME Interface 10–15