User guide

Table 10–5 VME Interface Processor Page Monitor CSR
Field Name Description
<2:0> Monitor 1 Number of access to page.
<3> Overflow Overflow for Monitor 1. When a counter overflows, it sets a bit in
VIP_BESR register. If enabled by the VIP_ICR register, the overflow
causes VIP_LIRQ<0> interrupt to be asserted at VIC_LIRQ<2>.
<6:4> Monitor 1 Number of access to page.
<7> Overflow Overflow for Monitor 1
<10:8> Monitor 1 Number of access to page.
<11> Overflow Overflow for Monitor 1
10.2.3 Interprocessor Communication
Digital Alpha VME 4 system’s VIC64 chip has two sets of registers,
communication registers and software switches, which allow communication
between processors. The use of these register sets are restricted to only one set
at a time.
The registers are accessible in the VME interface register space mapped in PCI
memory space. When accessed over the VMEbus, they are located in A16 space
by Byte 1 of the VMEbus i/f address base register (VIF_ABR). They are also
accessible from PCI memory space starting at address VME_IF_BASE + 0x60.
The interprocessor communication register map is shown in Table 10–6.
10.2.3.1 Interprocessor Communication Registers
Five of the general-purpose registers, the interprocessor communication registers
(ICRs), are simply 8-bit read/write registers accessible over the VMEbus and in
local PCI memory space. Two others allow VIC64 status and hardware revision
information to be read over the VMEbus.
Bits <4:0> in the final register are set when there is a write access to the
corresponding ICR. See the VIC64 specification for more detail.
10.2.3.2 Interprocessor Communication Global Switches
The Interprocessor Communication Global Switches (ICGSs) are software
switches that may be set over the VMEbus (not locally accessible over the PCI
bus) to interrupt a group of VMEbus modules that share an A16 base address.
10–14 VME Interface