User guide

Because the VMEbus specification prohibits crossing any 256/2 KB boundaries,
any DMA must split into a number of bus transfers. At the interval between
these transfers, the VME interface can be programmed to wait a period of time
before arbitrating again for the VMEbus and proceeding. This delay gives slave
accesses to the Digital Alpha VME 4 the opportunity to complete during a block-
mode transfer. This interleave period is programmable in the VIC block transfer
control register, shown in Figure 10–5. Table 10–2 describes the register fields.
Figure 10–5 VIC Block Transfer Control Register
31 07 06 05 04 03 00
ML013329
Block-Mode Enable
DMA Direction
1 -> Read
0 -> Write
Don't Care
VME_IF_BASE+D4 :
Interleave Period (250 x value)nS
VIC_BTCR
0
08
0
Table 10–2 VIC Block Transfer Control Register
Field Name Description
<3:0> Interleave
period
250xValue nanoseconds. Specifies a delay between bus transfers of
blocks to allow arbitration of the bus.
<4> DMA
direction
When set, the direction is Read. When clear, the direction is Write.
<5> Not used.
<6> Block-mode
enable
When set, block mode is enabled. When clear, block mode is
disabled.
The transfer burst length on the VMEbus can be programmed to be less than
the maximum 256/2K burst, using the DMA burst length field of the VIC release
control register (see Figure 10–12).
A block transfer setup consists of defining the:
• Data size
• Transfer direction
• Transfer length in bytes (must be even as D08 block mode is not supported)
10–8 VME Interface