User guide

The two accesses are handled as an indivisible sequence on the VMEbus by
acquiring VMEbus ownership for the current access and holding it until another
master operation is done by the processor. This is designed for doing atomic
VMEbus RMW cycles.
The VIC interface configuration register must be programmed with VIC_
ICR<7:5> = 001. A value of VIC_ICR<7:5> = 000 disables the RMW mode
regardless of the setting in the scatter-gather map, while any other VIC_
ICR<7:5> value gives UNPREDICTABLE results.
To use the RMW mechanism, software must be able to guarantee sequential
execution of the two PCI cycles to the VMEbus on the PCI bus.
An alternate way of defining a divisible sequence is to use the VIC64 ‘‘bus capture
and hold’’ mechanism, described in Section 10.3.1.
10.1.2 Data Transfers
As a master, data transfers are supported in two ways:
Single transfers: D08, D16, D32 data size
Block transfers: D16, D32, D64 data size
10.1.2.1 Single Mode Transfers
Single D08, D16, and D32 data transfers are executed by individual accesses to
either of the two VME address windows in PCI memory space. The data size for
the VME transfers are derived from the byte-enabling of the corresponding PCI
cycle.
10.1.2.2 Block Mode Transfers
A block-mode DMA engine in the VME interface can be programmed to transfer
up to 64 KB without processor intervention in D16, D32, or D64. The interface
handles the segmentation of the transfer so as not to violate the VMEbus
specification for crossing VME address boundaries.
The following restrictions apply to master block-mode transfers:
• Master block mode D64 transfers that do not start on naturally-aligned 2K
boundaries on the VMEbus require some special care. If a 2 KB boundary
crossing is enabled (VIC_BTDR<7> = 1), the VME starting address must be
aligned to a 2 KB boundary.
• The PCI address must not cross a 64 KB aligned boundary. Usually, the
operating system’s DMA interface handles this restriction.
VME Interface 10–7