User guide

Table 9–19 Watchdog Timer TOY Clock Command Register
Field Name Type Description
<0> Not used
<1> Watchdog timer flag R/W
<2> Not used
<3> Watchdog timer enable R/W
<4> Pulse/level O/P R/W
<5> Watchdog timer assertion R/W
<6> Watchdog timer select R/W
<7> Transfer enable R/W See description of TOY
clock.
Because there exists the possibility to set up the watchdog timer in such a way
that it would constantly drive the module into reset (by setting the watchdog
timer output to level rather than pulse, for example), an external enable, which
defaults to disabled on power-up, is included. This bit is in the module control
register (see Figure 9–19), and described in Section 9.2.7. When the watchdog
timer has been fully and correctly initialized, this bit should be set to allow
normal watchdog timer operation.
Figure 9–19 Watchdog Timer Module Control Register
31 08 07 06 05 04 00
ML013301
Watchdog Enable
Don't Care
MOD_CNTRL_REG :
The reset generated by the watchdog timer is ‘‘one-shot,’’ because the module
control register is cleared, disabling the watchdog timer reset, when the hardware
reset is asserted.
Nbus 9–35