User guide

(general-purpose registers (GPRs), and so forth) at the time the watchdog timer

expires before the full hardware reset.

Watchdog timer operation is controlled by four registers - three in the DS1386

chip and a single enable bit in the module control register. Operation of the

watchdog timer must be conﬁgured in the TOY clock command register (TOY_

BASE_ADDR+0x0B) and enabled in the module control register (MOD_CNTRL_

REG).

The watchdog timer timeout time is set in BCD in two bytewide registers in the

TOY clock’s address space, as shown in Figure 9–17.

Figure 9–17 Watchdog Timer Registers

07 06 05 04 03 02 01 00

1/10 Sec 1/100 Sec

Second

TOY_BASE_ADDR + 0C :

TOY_BASE_ADDR + 0D :

ML013299

Within the TOY clock chip, the interrupt line and the pulse/level assertion of that

interrupt line for the watchdog timer are selectable. In addition, the watchdog

function can be enabled or disabled by the TOY clock command byte, bit <4>.

Figure 9–18 shows the required setup of the watchdog timer.

Figure 9–18 Watchdog Timer TOY Clock Command Register

31 08 07 06 05 04 03 02 01 00

ML013300

Transfer Enable

Watchdog INT Select

Don't Care

TOY_BASE_ADDR + 0B :

Pulse(1)/Level O/P

Watchdog Disable

Watchdog Flag (RO)

9–34 Nbus