User guide

9.7.4 Interrupts
The expiration of timers #0 and #2 are recorded in a timer status register. The
asserted state of either or both of the timer status bits can be enabled to assert
an interrupt request.
The active low outputs of timer #1 and #2 are routed to P2 connector pins. The
active low clock and gate inputs of timer #0 are also tied to P2 connector pins.
TMR1_EXT_OPL=P2pinC12(timer #1 output)
TMR2_EXT_OPL=P2pinC11(timer #2 output)
TMR_MINOR_IP L = P2 pin C13 (timer #0 clock input)
TMR_MAJOR_IP L = P2 pin C14 (timer #0 gate input)
Figure 9–15 shows the timer inputs and outputs.
Figure 9–15 Timer Clocking
ML013297
Tmr1_ext_op L
(P2 pin C12)
Tmr2_ext_op L
(P2 pin C11)
Clk
Gat
Timer
Clk
Gat
Timer
Clk
Gat
Timer
Tmr_irq
+5
Tmr_minor_ip L
(P2 pin C13)
+5
10MHz
+5
Tmr_major_ip L
(P2 pin C14)
The clock inputs to timer #1 and #2 are a fixed 10 MHz source. The clock input
of timer #0 is from a P2 pin (TMR_MINOR_IP L) only.
The gate inputs for timers #1 and #2 are permanently asserted. This means that
82C54 modes 1 and 5 are disabled on timers #1 and #2.
The timer #0 gate input is driven from P2 pin C13 through synchronization and
edge detect logic. This signal conditioning means that when the gate input to the
module makes a high-to-low transition, a synchronized single clock-tick pulse is
presented to the gate input of the 82C54 (see details of the 26V12 PAL for exact
timing information associated with this gate function).
The main timer interrupt request line from timers #0 and #2 through the timer
interrupt status register logic is routed to interrupt register 2<5>.
Nbus 9–31