User guide

The timer output is initially high. When the timer value is written, the
output is driven low. The counter decrements to 0 where it drives the output
high.
• Mode 1 - Hardware Retriggerable One-Shot
This mode allows a value to be written to the timer that can be used when
a hardware trigger has been received. TMR_MAJOR_IP L (P2 pin C14)
transitions from a high to a low.
If a new count value is written to the counter during a one-shot pulse, the
current one-shot is not affected unless the counter is retriggered. In that case,
the counter is loaded with the new count and the one-shot pulse continues
until the new count expires.
The timer output is initially high. A trigger results in loading the counter
and setting the output low on the next clock pulse, starting the one-shot. An
initial count of n results in a one-shot pulse of n clock cycles in duration. The
output is driven high when the counter reaches 0.
The one-shot is retriggerable. The output remains low for n clocks after any
trigger. The one-shot pulse can be repeated without rewriting the same count
into the counter.
• Mode 3 - Continuous, Square Wave Output
This mode generates a square wave output of period n clock ticks. This output
is usually used to generate a rate output or a regular interrupt request to the
CPU. For odd count values, the output is high for (n+1)/2 and low for (n-1)/2
counts. A count value of 1 is illegal.
For timer #0, the gate input in this mode has a synchronizing or reset effect.
If the gate goes low, the counter is reloaded with its original value and the
counting restarts.
• Mode 5 - Hardware Triggered Strobe
Placing timer #0 in this mode generates a single clock wide pulse delayed
by n+1 clock cycles. The output is initially high. Counting is triggered by
a high-to-low transition of TMR_MAJOR_IP L (P2 pin C14). The output of
timer #0 goes low for one clock period after n+1 clock pulses. The counting
sequence is retriggerable. Timer #0’s output does not strobe low for n+1
clocks after any strobe.
9–30 Nbus