User guide

Figure 9–14 82C54 Timer Data Access
ML013296
Data Rd/Wr (byte)
Mode 01 or 11?
Mode 11?
MSB
No
"Signal Done"
Yes
LSB
Data Rd/Wr (byte)
Yes
No
9.7.2 Timer Registers
Each timer element is a 16-bit synchronous down counter. The device asserts
or pulses the corresponding output pin when a counter reaches a 0 count. The
following timers are identical in function but are fully independent:
• Timer #0 must be clocked externally by P2 pin C13. Optionally, its gate
input can also be driven by P2 pin C14. When Timer #0 makes a low-to-high
transition, its output causes the assertion of an interrupt request (IRQ). The
IRQ can be dismissed by an access to the timer interrupt status register.
• Timer #1 operates as a rate generator with its output being driven off module
by P2 pin C12. This timer is clocked by a fixed 10 MHz. The output is also
routed directly to VIC local IRQ input <3>.
• Timer #2 operates as a rate generator with its output connected to P2 pin
C11. This timer is clocked with the same fixed 10 MHz. The output can also
be used on the module to generate an interrupt request. If enabled, Timer
#0’s output during a transition from low-to-high causes the assertion of an
9–28 Nbus