User guide

Table 9–15 Timer Interface Registers

Field

TMR_BASE_ADDR = 4000 Description

<7:0> TMR_BASE_ADDR+00 Timer#0 Register

TMR_BASE_ADDR+04 Timer#1 Register

TMR_BASE_ADDR+08 Timer#2 Register

TMR_BASE_ADDR+0C Control Register

TMR_BASE_ADDR+10 Interrupt Status Register

TMR_BASE_ADDR+14 Interrupt Status Register

To program the timer device for initialization or during normal operation, the

control byte (TMR_BASE_ADDR + 0x0C) is written. To access (read or write)

the individual timer count values, the separate timer data registers are used

(TMR_BASE_ADDR +0x00 to +0x08).

9.7.1 Interval Timing Control Register

In the interval timing control register, the control byte shown in Figure 9–13,

deﬁnes the mode of operation of and provides access control to each individual

timer.

Because only a single byte in the 82C54 address space is used to access the full

16-bit counter value, two accesses are required to operate on the full 16 bits. The

access can use least-signiﬁcant bit, most-signiﬁcant bit, or both.

Figure 9–13 82C54 Control Byte

31 08 07 06 05 04 03 02 01 00

ML013295

Timer #

Latch Count

Don't Care

TMR_BASE_ADDR + 0C :

011 Continuous

000 Single Shot

Binary 0/BCD 1

9–26 Nbus