User guide

Table 9–9 Bcache Size and Speed Decode

<2> <1> <0> Bcache Size Bcache Speed

0 0 0 Disables Bcache

0 0 1 512 KB 15 ns

0 1 0 2 MB 12 ns

0 1 1 Reserved for future use

1 0 0 Reserved for future use

1 0 1 Reserved for future use

1 1 0 Reserved for future use

1 1 1 Reserved for future use

9.3 ROM

The system has two ROM structures:

• Serial ROM (SROM)

Contains 8 KB of code serially loaded into the 21064A chip’s internal cache

(Icache) on power-up. This 8 KB of SROM is copied into the processor

instruction cache during a reset. Execution control is passed to this code in

PAL mode. The function of the SROM code is as follows:

Verify the processor operation

Identify the reset type

Find 2 MB of good memory

Check the ability to read system ROM (checksum)

Decompress 512 KB of ROM (initialization code) into memory

Transfer control to initialization code

The SROM is socketed to allow future ﬁrmware upgrades.

• System ROM (ﬂash)

CPU address = 0x200000000

PCI sparse memory address = ROM_BASE_ADDR = 0x00000000

The ﬂash ROM is accessible as a contiguous 1 MB in PCI memory space.

Only byte accesses to the ROM are supported. The ﬁrst 512 KB of ﬂash ROM

are reserved for console use (Figure 9–11). The remaining space in the ﬂash

ROM is reserved for onboard user code. Since the system has a total of 4 MB

of ﬂash ROM, the ROM is segmented into 1 MB windows using bits <1:0> of

the module control register.

Nbus 9–17