User guide

Table 9–8 (Cont.) Module Control Register
Field Name Type Description
<5> Watchdog Timer
Reset Enable
When 0, watchdog timer expiration has no
effect. If set, and the DIP bit of the reset
reason register is cleared, a watchdog timer
expiration generates a hardware reset of the
module. Reset default is disabled.
<6> Undefined/reserved
<7> Timer 0 Mode 1
Enable
Default at power-up is 0. When 0, Timer 0
in the 82C54 can only operate in modes 0
and 3. When set, the polarity of the TIMER0
gate input of the 8254 timer chip is inverted,
allowing proper operation in modes 1 and 5.
9.2.8 Bcache Configuration Register
CPU address: 0x1C00101E0
Nbus offset: 0x80F
The Bcache configuration register shows the size and speed of the backup cache.
The values in this register are determined at installation by setting jumper J10
on the CPU board. This is a read-only register.
Figure 9–10 Bcache Configuration Register
31 08 07 03 02 00
ML013313
Reserved
BC Configuration
Don't Care
BCACHE_CONFIG_REG :
9–16 Nbus