User guide

Figure 9–9 Module Control Register 1
31 08 07 06 05 04 03 02 01 00
ML013289
Timer 0 Mode Enable
Undefined
Don't Care
MOD_CNTRL_REG_1 :
Watchdog Reset Enable
Undefined
Flash Switch
Flash Write Enable
Flash Select
Flash Address 20
Table 9–8 Module Control Register
Field Name Type Description
<1:0> Flash Address 20
Flash Select
Divide flash ROM into four 1 MB windows.
Flash Select divides the ROM into two 2 MB
segments and Flash Address 20 divides the
segments in half.
These two bits default to <00> at power-up,
selecting the device containing the console
image in the bottom 512 KB. The remaining
3.5 MB is available for user flash.
<2> Flash Write Enable Default at power-up is 0. When set to 1,
this bit asserts write enable to the four flash
ROMs to allow updates. To avoid corrupting
the flash ROMs, keep this bit cleared (0)
when not updating.
<3> Flash Switch Read
only
Indicates the state of the flash ROM update
DIP switch. When set, flash ROM updates
are enabled. When clear, the flash Write
Enable bit is not allowed to enable writes to
flash.
<4> Undefined
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Nbus 9–15