User guide

Table 9–7 (Cont.) Reset Reason Registers

Field Name Type Description

<2> VME reset 0x80A : R/W to

clear

0x80E : Read

Only

82E : R/W to set

If set, it indicates that the module received

a VME reset.

<3> Power-up 0x80A : R/W to

clear

0x80E : Read

Only

82E : R/W to set

If set, all other bits are ignored.

<4> DIP 0x80A : Read

Only

0x80E : Read

Only

82E : R/W to set

If set, Digital Alpha VME 4 does not reset.

9.2.6 Heartbeat Register

CPU Address: 0x1C0010180

Nbus offset: 0x80C

When the heartbeat clock is enabled in the TOY clock chip, each active (low to

high, at a frequency of 1024 Hz) transition sets the heartbeat status bit. This bit

is not directly readable but it drives the heartbeat interrupt line into interrupt

Writing (data independent) to the heartbeat (clear-interrupt) register clears the

heartbeat status bit and dismisses the interrupt request.

9.2.7 Module Control Register 1

CPU address: 0x1C00101A0

Nbus offset: 0x80D

The module control register 1 is a read/write register for controlling miscellaneous

module functions. This register is reset to 0 on any system reset. Figure 9–9

shows the module control register 1.

9–14 Nbus