User guide

These registers are read/pseudowritable registers located at a fixed address on
Nbus in PCI I/O address space. Register 1 is located in Nbus offset 0x80A but
is also aliased in two longwords at 0x80E and 0x82E. The register contains
four reset status bits and one diagnostics in progress (DIP) bit. In reset reason
register 3, at 0x82E, any write operation sets <4:0>. This is for testing only.
Figure 9–8 Reset Reason Registers
ML013290
DIP Bit
Power-Up
Don't Care
82E :
VME Reset
Front Panel Switch
Watchdog
Don't Care
80E :
31 05 04 03 02 01 00
Don't Care
80A :
R/WC
RO
R/WS
RO = Read Only
R/W = Read/Writable
R/WC = Readable/Write to Clear
R/WS = Readable/Write to Set
Table 9–7 Reset Reason Registers
Field Name Type Description
<0> Watchdog timer 0x80A : R/W to
clear
0x80E : Read
Only
82E : R/W to set
This is set immediately when a watchdog
timer timeout occurs. Available to indicate
the HALT reason before the system actually
resets. In this case, the register forms
part of the halt reason information in the
system.
<1> Front Panel
Switch
0x80A : R/W to
clear
0x80E : Read
Only
82E : R/W to set
If set, it indicates that the front panel
switch caused a reset.
(continued on next page)
Nbus 9–13