User guide

Table 9–5 ID Bits

Bit ID Bit Description

<6,4,2,0> ID 0 Used to deﬁne memory DIMM conﬁguration (see Table 9–6).

<7,5,3,17> ID 1 Sets the refresh mode, according to the following values:

0 Normal

1 Self refresh

Table 9–6 Memory DIMM Conﬁguration Bit

PD8 IDO Description

1 0 x64

1 1 x72 Parity

0 0 x72 ECC

0 1 x80 ECC

9.2.5 Reset Reason Registers

• Reset reason 1

CPU address: 0x1C0010140

Nbus offset: 0x80A

• Reset reason 2

CPU address: 0x1C00101C0

Nbus offset: 0x80E

• Reset reason 3

CPU address: 0x1C00105C0

Nbus offset: 0x82E

The reset reason registers record the cause of a module reset. The cause can be

one of the following:

• Power-up

• VME reset

• Front panel switch

• Watchdog timer

9–12 Nbus