User guide

Table 9–4 Presence Detect
Bit PD Bit Description
<3:0> PD 4-1
PD Bits
4321
Configuration
(Parity/ECC)
DRAM
Organization
RE
Address
CE
Address
Refresh
Periods (ms)
Normal Slow
0 1 0 0 1M x 72/80 1M x 4/16 10 10 16 128
0 1 0 1 2M x 72/80 1M x 4/16 10 10 16 128
1 0 1 1 4M x 72 4M x 4 12 11 64 256
1 0 1 1 4M x 80 4M x 4 12 10 64 256
<4> PD 5 Controls data mode access, according to the following values:
PD5 Definition
0 Fast page
1 Fast page with EDO
<6:5> PD 7-6 Controls speed, according to the following values:
PD 7 PD 6 Speed
0 1 80 ns
1 0 70 ns
1 1 60 ns
0 0 50 ns
0 1 40 ns
<7> PD 8 Used to define memory DIMM configuration (see Table 9–6).
Nbus 9–11