User guide

These registers are read-only. The values are loaded from memory DIMMs,
identified in Table 2–8 at power-up. A complete description of the memory
DIMMs is in Chapter 6.
Table 9–3 DIMM Identification
DIMM J# DRAM# Bank# Memory Configuration Register
2000
3101
4113
5012
DRAM0 refers to the DIMM array containing memory data lines 0 - 63.
DRAM1 refers to the DIMM array containing memory data lines 64 - 127.
Tables 9–4 and 9–5 show the decode of the presence detect and ID bits stored in
these registers.
Figure 9–6 Memory Configuration Registers 0-3
31 08 07 06 05 04 03 02 01 00
ML013315
Presence Detect Bits 1-8
Don't Care
MEM_CONFIG_0 :
MEM_CONFIG_1 :
MEM_CONFIG_2 :
MEM_CONFIG_3 :
Nbus 9–9