User guide

Table 9–2 (Cont.) Module Conﬁguration Register

Field Name Type Description

<6:5> CPU ID RO Determine the speed of the CPU according to the following

table:

<6:5> Deﬁnition

00 224 MHz

01 288 MHz

10 Reserved

11 Reserved

9.2.3 Interrupt and Interrupt Mask Registers 1, 2, 3, 4

See Chapter 11 for descriptions of these registers.

9.2.4 Memory Conﬁguration Registers 0, 1, 2, 3 and Memory

Identiﬁcation Register

• Memory conﬁguration 0

CPU address: 0x1C00100C0

Nbus offset: 0x806

• Memory conﬁguration 1

CPU address: 0x1C00100E0

Nbus offset: 0x807

• Memory conﬁguration 2

CPU address: 0x1C0010100

Nbus offset: 0x808

• Memory conﬁguration 3

CPU address: 0x1C0010120

Nbus offset: 0x809

0x1C0010160

0x80B

The memory conﬁguration and memory identiﬁcation registers store the presence

detect (PD) bits and the ID bits of the main memory DIMMs as shown in Figures

9–6 and 9–7.

9–8 Nbus