User guide

Register CPU Address Nbus Offset
Module display control 1 C001 0000 800
Module configuration 1 C001 0020 801
Interrupt register 1 1 C001 0040 802
Interrupt register 2 1 C001 0060 803
Interrupt register 3 1 C001 0080 804
Interrupt register 4 1 C001 00A0 805
Memory configuration 0 1 C001 00C0 806
Memory configuration 1 1 C001 00E0 807
Memory configuration 2 1 C001 0100 808
Memory configuration 3 1 C001 0120 809
Reset reason 1 1 C001 0140 80A
Memory identification 1 C001 0160 80B
Heartbeat (clear-interrupt) 1 C001 0180 80C
Module control 1 C001 01A0 80D
Reset reason 2 1 C001 01C0 80E
Bcache configuration 1 C001 01E0 80F
Reset reason 3 1 C001 05C0 82E
9.2.1 Module Display Control Register
CPU address: 0x1C0010000
Nbus offset: 0x800
The display is a 5x7 dot-matrix intelligent display device, with 96 characters. The
unit is read/writable by the display control register (MOD_DISP_REG), shown in
Figure 9–3.
Nbus 9–5