User guide

9.1.1.2 ISA Controller Recovery Timer Register
The ISA controller recovery timer register (offset +4Ch) is one of two bytewide
registers used as the Nbus control word.
The I/O recovery mechanism in the SIO chip is used to add recovery delay
between the I/O cycles originating in the PCI bus and directed to the Nbus. Since
only 8-bit cycles are supported, only bits <6:3> of the register are significant.
Bits <6:3> define the number of system-clock ticks inserted between back-to-back
cycles. The required value for Digital Alpha VME 4 is 1001, representing one
additional system-clock tick.
9.1.1.3 ISA Clock Divisor Register
The ISA clock divisor register (offset +4Dh) is one of two bytewide registers used
as the Nbus control word. This register enables positive decode for BIOS ROM
and the PCI-to-ISA clock divisor. For Digital Alpha VME 4, the BIOS ROM
region must not be positively decoded.
Bit <6> must be cleared and bits <2:0> must be 000 for a 32 MHz PCI system.
All other bits must be 0.
9.2 Module Registers
There are 17 miscellaneous registers implemented in module logic for a variety of
read/write functions. These registers are located in PCI Sparse I/O space within
the SIO chip address block and are listed in the following table.
9–4 Nbus