User guide

Figure 9–2 SIO Configuration Block
Reserved
PCI Control
MEMCS# Control (not used)
ISA Addr Decode (not used)

Reserved
MEMCS# Attributes (not used)

Reserved
Device ID = 0484h
Status
Vendor ID = 8086h
Command
Class Code Rev ID
: 00004000
: 00004004
: 00004008
: 0000400C to 0000403F
: 00004040
: 00004044
: 00004048
: 0000404C
: 00004050
: 00004054
: 00004058 to 000040FF
ML013285
ISA Bus Control
9.1.1.1 PCI Control Register
The PCI control register enables the SIO chip to respond to PCI IACK cycles and
to set the expected assertion speed of the DEVSEL# signal so that the subtractive
decode sample point can be set. The PCI posted write buffer is also enabled.
Table 9–1 lists the fields of the PCI control register.
Table 9–1 PCI Control Register
Field Name Description
<5> Must be set to a 1 (default)
<4:3> Must be set to <00> to allow slow sample point
timing for negative decode.
<2> PCI Posted Write Buffer Enable Must be set to 1.
All other bits must be 0.
Nbus 9–3