User guide

Table 8–2 SCSI Controller CSRs
Label R/W Description Offset
SCNTL0 R/W SCSI Control 0 00
SCNTL1 R/W SCSI Control 1 01
SCNTL2 R/W SCSI Control 2 02
SCNTL3 R/W SCSI Control 3 03
SCID R/W SCSI Chip ID 04
SXFER R/W SCSI Transfer 05
SDID R/W SCSI Destination ID 06
GPREG R/W General Purpose 07
SFBR R/W 1st Byte Rx’ed 08
SOCL R/W Output Cntrl Latch 09
SSID R Selector ID 0A
SBCL R/W Bus Control Lines 0B
DSTST R DMA Status 0C
SSTAT0 R SCSI Status 0 0D
SSTAT1 R SCSI Status 1 0E
SSTAT2 R SCSI Status 2 0F
DSA R/W Data Structure Addr 10-13
ISTAT R/W Interrupt Status 14
RESERVED 15-17
CTEST0 R/W Chip Test 0 18
CTEST1 R Chip Test 1 19
CTEST2 R Chip Test 2 1A
CTEST3 R Chip Test 3 1B
TEMP R/W Temporary Stack 1C-1F
20
CTEST4 R/W Chip Test 4 21
22
CTEST6 R/W Chip Test 5 23
DBC R/W DMA Byte Counter 24-26
(continued on next page)
PCI bus 8–9