User guide

Figure 8–4 PCI Configuration Block
I/O Base Address (SCSI_IO_BASE)
Memory Base Address (SCSI_MEM_BASE)

Reserved
Reserved
N/S (=Not Supported)
Reserved
Reserved


Operating registers mapped to bytes 80h to FFh.
Device ID = 0001h
Status
Vendor ID = 1000h
Command
Class Code Rev ID
N/SN/S Don't Care Latency Timer
XX
: 00002000
: 00002004
: 00002008
: 0000200C
: 00002010
: 00002014

: 00002028
: 0000202C
: 00002030
: 00002034
: 00002038
: 0000203C

: 00002040 to 000020FC
ML013284
XX
8.2.5 SCSI Control Status Registers
The SCSI controller has 128 accessible bytewide CSRs, as shown in Table 8–2.
These registers are accessible starting at the following addresses:
• SCSI_IO_BASE in PCI I/O space
• SCSI_MEM_BASE in PCI memory space
For information about how to program these registers, see the PCI local bus
specification.
8–8 PCI bus