User guide

Table 8–1 Ethernet Controller CSRs
Register Meaning Address
CSR0 Bus mode register xxxx xx00H
CSR1 Transmit poll demand xxxx xx08H
CSR2 Receive poll demand xxxx xx10H
CSR3 Rx list base address xxxx xx18H
CSR4 Tx list base address xxxx xx20H
CSR5 Status register xxxx xx28H
CSR6 Serial command register xxxx xx30H
CSR7 Interrupt mask register xxxx xx38H
CSR8 Missed frame register xxxx xx40H
CSR9 ENET ROM register xxxx xx48H
CSR10 Reserved xxxx xx50H
CSR11 Full-duplex register xxxx xx58H
CSR12 SIA status register xxxx xx60H
CSR13 SIA connectivity register xxxx xx68H
CSR14 SIA Tx Rx register xxxx xx70H
CSR15 SIA general register xxxx xx78H
8.1.3 PCI Cycles
As a slave, the Ethernet controller responds to single longword accesses in I/O
space and configuration space. Burst writes to I/O space cause target-initiated
retry termination of the cycle.
As a master, the Ethernet controller performs DMA operations. Its tenure on the
PCI bus can be programmed by the burst length in the bus mode register (CSR0)
and by the PCI latency timer value in the configuration latency timer register.
The Ethernet controller handles the following types of cycle termination:
• Target-initiated retry
• Abort
• DEVSEL abort
Target-aborted terminations cause an interrupt.
PCI bus 8–5