User guide

Table 7–12 TLB Data Registers 0 Through 7
Field Name Type Description
<31:21> Reserved MBZ —
<20:1> CPU_PAGE<32:13> RO CPU page. Bits <32:13> of the translated
CPU address can be read or written through
this field.
<0> Reserved MBZ —
7.5.14 Translation Buffer Invalidate All Register: 0x1A0000400
The translation buffer invalidate all register (TBIA) is write-only. A write
transaction to this register invalidates all valid entries in the scatter-gather map
TLB.
7–22 PCI Host Bridge