User guide

Figure 7–13 TLB Tag Registers 0 Through 7: 0x1A0000200 to 0x1A00002E0
31 30 08 07 06 05 04 03 02 01 00
LJ-04205.AI
PCI_PAGE<31:13>
EVAL
091011121314151617181920212223242526272829
MBZ
Table 7–11 TLB Tag Registers 0 Through 7
Field Name Type Description
<31:13> PCI_PAGE<31:13> RO PCI page. Specifies the PCI page address
(tag) for the translated CPU page address in
the associated TLB data register.
<12> EVAL RO Entry valid. The entry valid bit can be read
and written through this bit. Normally, the
invalid bit contains the value read during a
page table entry read transaction.
<11:0> Reserved MBZ —
7.5.13 TLB Data Registers 0 Through 7
The TLB data registers contain the CPU page address associated with the PCI
page address in the TLB tag registers. The registers are shown in Figure 7–14
and are defined in Table 7–12.
Figure 7–14 TLB Data Registers 0 Through 7: 0x1A0000300 to 0x1A00003E0
31 30 08 07 06 05 04 03 02 01 00
LJ-04206.AI
MBZ
CPU_PAGE<32:13>
091011121314151617181920212223242526272829
MBZ
PCI Host Bridge 7–21