User guide

7.5.11 PCI Master Latency Timer Register
The PCI master latency timer register defines the latency timer period. Define a
nonzero value during system configuration. The register is shown in Figure 7–12
and is defined in Table 7–10.
Figure 7–12 PCI Master Latency Timer Register: 0x1A00001E0
31 30 08 07 06 05 04 03 02 01 00
LJ-04204.AI
MBZ
PMLC<7:0>
091011121314151617181920212223242526272829
Table 7–10 PCI Master Latency Timer Register
Field Name Type Description
<31:8> Reserved MBZ —
<7:0> PMLC<7:0> — PCI master latency time. Loaded into the
master latency timer register at the start
of a PCI master transaction initiated by the
21071-DA. The register resets to zero.
7.5.12 TLB Tag Registers 0 Through 7
The TLB tag registers contain the PCI page address associated with the CPU
page address in the TLB data registers. The registers are shown in Figure 7–13
and are defined in Table 7–11.
7–20 PCI Host Bridge