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Table 7–8 Host Address Extension Register 1

Field Name Type Description

<31:27> EADDR<4:0> RW, 0 Extension address. This ﬁeld is used as the

ﬁve high-order PCI address bits (ad<31:27>)

for CPU-initiated transactions to PCI

memory.

<26:0> Reserved MBZ —

7.5.10 Host Address Extension Register 2

The host address extension register 2 generates ad<31:24> on CPU-initiated

transactions addressing PCI I/O space. It also generates ad<1:0> during PCI

conﬁguration read and write transactions. The register is shown in Figure 7–11

and is deﬁned in Table 7–9.

Figure 7–11 Host Address Extension Register 2: 0x1A00001C0

31 30 08 07 06 05 04 03 02 01 00

LJ-04203.AI

EADDR<7:0>

MBZ

091011121314151617181920212223242526272829

CONF_ADDR<1:0>

Table 7–9 Host Address Extension Register 2

Field Name Type Description

<31:24> EADDR<7:0> RW, 0 Extended address. Used as the eight high-

order PCI address bits ad<31:24> for CPU-

initiated transactions to PCI I/O space.

<23:2> Reserved MBZ —

<1:0> CONF_ADDR<1:0> RW, 0 Conﬁguration address. Used as the two

low-order PCI address bits ad<1:0> for CPU-

initiated transactions to PCI conﬁguration

space.

PCI Host Bridge 7–19