User guide

Table 7–7 PCI Mask Registers 1 and 2
Field Name Type Description
<31:20> PCI_MASK<31:20> RW PCI mask. This field specifies the size of
the PCI target window; it is also used in the
PCI-to-CPU address translation.
<19:0> Reserved MBZ —
7.5.8 Host Address Extension Register 0
The host address extension register is hardcoded to zero. A read transaction from
this register returns zero; a write transaction has no effect. The register is shown
in Figure 7–9.
Figure 7–9 Host Address Extension Register 0: 0x1A0000180
31 30 08 07 06 05 04 03 02 01 00
LJ-04201.AI
Hardcoded to Zero
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7.5.9 Host Address Extension Register 1
The host address extension register 1 generates ad<31:27> on CPU-initiated
transactions addressing PCI memory space. The register is shown in Figure 7–10
and is defined in Table 7–8.
Figure 7–10 Host Address Extension Register 1: 0x1A00001A0
31 30 08 07 06 05 04 03 02 01 00
LJ-04202.AI
EADDR<4:0>
MBZ
091011121314151617181920212223242526272829
7–18 PCI Host Bridge