User guide

Table 7–6 (Cont.) PCI Base Registers 1 and 2

Field Name Type Description

<19> WENB RW, 0 Window enable. When clear, the PCI target

window is disabled and does not respond to

PCI-initiated transfers. When set, the PCI

target window is enabled and responds to

PCI-initiated transfers that hit in the address

range of the target window. This bit must

be disabled by the processor when modifying

any of the PCI target window registers (base,

mask, or translated base).

<18> SGEN RW, 0 Scatter-gather enable. When clear, the

PCI target window uses direct mapping to

translate a PCI address to a CPU address.

When set, the PCI target window uses

scatter-gather mapping to translate a PCI

address to a CPU address.

<17:0> Reserved MBZ —

7.5.7 PCI Mask Registers 1 and 2

PCI mask registers 1 and 2 deﬁne the size of the target window. The registers

are shown in Figure 7–8 and are deﬁned in Table 7–7.

Figure 7–8 PCI Mask Registers 1 and 2: 0x1A0000140, 0x1A0000160

31 30 08 07 06 05 04 03 02 01 00

LJ-04200.AI

PCI_MASK<31:20>

MBZ

091011121314151617181920212223242526272829

PCI Host Bridge 7–17