User guide

Table 7–5 Translated Base Registers 1 and 2

Field Name Type Description

<31:9> T_BASE<32:10> RW Translated base. If scatter-gather mapping

is disabled, T_BASE speciﬁes the base CPU

address of the translated PCI address for the

PCI target window. If scatter-gather mapping

is enabled, T_BASE speciﬁes the base CPU

address for the scatter-gather map table for the

PCI target window.

<8:0> Reserved MBZ —

7.5.6 PCI Base Registers 1 and 2

PCI base registers 1 and 2 provide the base address of the target window. The

registers are shown in Figure 7–7 and are deﬁned in Table 7–6.

Figure 7–7 PCI Base Registers 1 and 2: 0x1A0000100, 0x1A0000120

31 30 08 07 06 05 04 03 02 01 00

LJ-04199.AI

PCI_BASE<31:20>

WENB

091011121314151617181920212223242526272829

SGEN

MBZ

Table 7–6 PCI Base Registers 1 and 2

Field Name Type Description

<31:20> PCI_BASE<31:20> RW PCI base. Speciﬁes the base address of the

PCI target window.

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7–16 PCI Host Bridge