User guide

9–2 Module Configuration Register................... 9–7
9–3 DIMM Identification . . . ....................... 9–9
9–4 Presence Detect .............................. 9–11
9–5 ID Bits ..................................... 9–12
9–6 Memory DIMM Configuration Bit . ............... 9–12
9–7 Reset Reason Registers . ....................... 9–13
9–8 Module Control Register ....................... 9–15
9–9 Bcache Size and Speed Decode ................... 9–17
9–10 Super I/O Register Address Space Map ............ 9–19
9–11 Integrated Device Electronics Register Addresses .... 9–21
9–12 Keyboard and Mouse Controller Addresses . . . ...... 9–22
9–13 TOY Clock Timekeeping Registers . ............... 9–23
9–14 TOY Clock Command Register ................... 9–24
9–15 Timer Interface Registers....................... 9–26
9–16 Interval Timing Control Register . . ............... 9–27
9–17 Timer Modes . ............................... 9–29
9–18 Timer Interrupt Status Register . . ............... 9–32
9–19 Watchdog Timer TOY Clock Command Register ..... 9–35
10–1 Formation of Address Modifier Codes from
Scatter-Gather Entry . . . ....................... 10–6
10–2 VIC Block Transfer Control Register .............. 10–8
10–3 VME Address . ............................... 10–12
10–4 PCI Address . . ............................... 10–13
10–5 VME Interface Processor Page Monitor CSR . . ...... 10–14
10–6 Interprocessor Communication Register Map Through
VIF_ABR ................................... 10–15
10–7 Arbiter/Requester Configuration Register .......... 10–19
10–8 VIC Release Control Register .................... 10–20
10–9 VMEbus Transfer Timeout Register ............... 10–22
10–10 VIC Interrupt Request/Status Register ............ 10–24
10–11 VMEbus Interrupter Interrupt Control Register ..... 10–25
10–12 Swap Modes . . ............................... 10–26
10–13 PCI BE# to Local A1,0 and SIZ1,0 Translation for
Various Swap Modes . . . ....................... 10–29
10–14 Local Bus A1,0 and SIZ1,0 to PCI BE# Translation . . . 10–30
10–15 Access to PCI Memory Addresses. . ............... 10–31
10–16 VME_IF_BASE + ............................. 10–37
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