User guide

Table 7–4 System Bus Error Address Register
Field Name Type Description
<31:3> SYS_ERR<33:5> RO System bus error address. Stores the address
sent on system bus sysadr<33:5> as a result
of a DMA transaction. The field logs errors
indicated by the MERR, UMRD, or CMRD
bits in the DCSR, and is valid only when one
of these bits is set. If an error bit is set, a
subsequent error of the same type does not
update the address logged in this register and
the LOST bit is set in the DCSR.
<2:0> Reserved MBZ —
7.5.4 Dummy Registers 1 Through 3
Dummy registers 1 through 3 have no side effects on write transactions and
they return zero on read transactions. Use write transactions to these registers
to pack the CPU’s write buffers to prevent merging of sparse space I/O write
transactions. If this mechanism is used, software is not required to use memory
barrier instructions between write transactions.
7.5.5 Translated Base Registers 1 and 2
The translated base registers 1 and 2 provide the base address when mapping is
enabled or disabled. The registers are shown in Figure 7–6 and are defined in
Table 7–5.
Figure 7–6 Translated Base Registers 1, 2: 0x1A00000C0, 0x1A00000E0
31 30 08 07 06 05 04 03 02 01 00
LJ-04198.AI
T_BASE<32:10>
MBZ
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PCI Host Bridge 7–15