User guide

Table 7–2 (Cont.) Diagnostic Control/Status Register
Field Name Type Description
<6> LOST RWC, 0 Lost error. This bit is set by a 21071-DA error
condition when the address register for that error
is locked because of a previous error. In this case,
error information for the second error is lost. The
logged address information in the system bus Error
Address register or the PCI error address register
remains valid for the initial error condition.
<5> IORT RWC, 0 I/O retry timeout. This bit is set when a retry
timeout error occurs on CPU-initiated read or write
transactions on the PCI. Bits ad<31:0> are logged
in the PCI error address register.
<4> DPEC RW, 0 Disable parity error checking. When set, parity
checking is not performed on the PCI bus (address
and data cycles, DMA and I/O transactions). Parity
generation is not affected.
<3> DCEI RW, 0 Disable correctable error interrupt. When set,
correctable errors on DMA read data are not logged
in the CMRD bit (DCSR12), and the address is not
updated in the system bus error address register.
This bit determines only whether the error is logged
and if the processor is interrupted.
<2> PENB RWC, 0 Prefetch enable bit. When set, the system bus
master state machine enables prefetching on DMA
read transactions.
<1> Reserved MBZ —
<0> TENB RW, 0 TLB enable. When set, the entire TLB is enabled.
When cleared, the TLB is turned off and subsequent
scatter-gather read transactions do not result in
allocation of TLB entries. Entries that were valid
when the TENB bit was cleared remain valid. To
invalidate entries, software must write to the TBIA
register.
7.5.2 PCI Error Address Register
The PCI error address register holds the PCI address ad<31:0> that was being
used when an error happened. The register is shown in Figure 7–4 and is defined
in Table 7–3.
PCI Host Bridge 7–13