User guide

Table 7–2 (Cont.) Diagnostic Control/Status Register
Field Name Type Description
<17:16> D_
BYP<1:0>
RW, 0 Disable read bypass. Controls the order of PCI-
initiated memory read transactions with respect to
PCI-initiated memory write transactions. The three
modes are shown in the following table.
Value Mode Description
00 Full
bypass
PCI-initiated memory read
transactions bypass buffered
DMA write transactions if the
double hexword address of
the read transaction does not
match that of the buffered
write transactions. The
address comparison is done
across address bits <31:6>.
01 — Reserved
10 Partial
bypass
DMA read transactions
bypass buffered memory
write transactions, if the
address within the page does
not match that of the buffered
DMA write transactions. The
address comparison is done
across bits <12:6>.
11 No
bypass
DMA read bypassing
is disabled. DMA read
transactions are ordered
with respect to DMA write
transactions originating on
the PCI bus.
<15> MERR RW, 0 Memory error. Set when the PCI host bridge
receives an error code in the iocack<1:0> field
in response to a memory access. Bits sysadr<35:5>
are logged in system bus error address register bits
<31:4>. This bit is not logged if the system bus
error address register is locked by a previous error.
In this case, the lost error bit is set.
(continued on next page)
PCI Host Bridge 7–11