User guide

Table 7–1 (Cont.) DECchip 21071-DA CSR Addresses
Address
16
Register Name
1 A000 03E0 TLB 7 data register
1 A000 0400 Translation buffer invalidate all register (TBIA)
7.5 Description of CSRs
The CSRs are 16 bits wide and are addressed on cache-line boundaries. Write
transactions to read-only registers could result in UNPREDICTABLE behavior;
read transactions are nondestructive. Only bits <15:0> of each register are
defined. Only zeros should be written to unspecified bits within a CSR. CSRs are
initialized as shown in the Type column.
All CSRs are addressed on cache line boundaries, that is, address bits <4:2> must
be zero. In the implementation, address bits <27:11> are treated as a don’t care
state. Therefore, accesses to addresses with nonzero address bits <27:11> map to
the CSR address with address bits <27:11> equal to zero.
7.5.1 Diagnostic Control/Status Register
The diagnostic control/status register (DCSR) controls the operational and
diagnostic modes, and reports status and error conditions. The register is shown
in Figure 7–3 and is defined in Table 7–2.
PCI Host Bridge 7–9