User guide

7.3.7 Retry Timeout

The PCI host bridge implements a timeout mechanism to terminate CPU-initiated

transactions that do not complete on the PCI bus because of too many disconnects

or retries. When it initiates a CPU transaction on the PCI bus, the PCI host

bridge counts the number of times it is retried or disconnected. If the number

exceeds 2

, it ﬂags an error to the CPU and aborts the transaction.

7.3.8 PCI Master Timeout

The PCI Local Bus Speciﬁcation speciﬁes a mechanism to limit the duration of

a PCI bus master’s burst sequence. The mechanism requires a PCI master to

implement a latency timer that counts the number of cycles since the assertion

of a frame#. If the master latency timer has expired, the master is required to

surrender the bus. The PCI host bridge implements a programmable master

latency timer.

This mechanism is intended to prevent masters from holding bus ownership for

extended periods of time, and selects low latency instead of high throughput.

7.3.9 Address Stepping in Conﬁguration Cycles

To provide ﬂexibility and reduce design complexity when using the address-

stepping feature, the PCI host bridge performs address stepping on conﬁguration

read and write transactions. For these transactions, the PCI host bridge drives

the PCI bus for two clock cycles during the address phase for the idsel# pins of

all PCI devices to reach a valid logic level. The PCI host bridge does not perform

address or data stepping in any other case.

7.4 Address Space of Control/Status Registers

CPU address: 0x1A0000000 through 0x1AFFFFFFF

This section describes the control/status registers (CSRs) of the DECchip 21071-

DA. The DECchip 21071-DA responds to all accesses in this space. Table 7–1

speciﬁes the registers and associated register addresses.

Table 7–1 DECchip 21071-DA CSR Addresses

Address

1 A000 0000 21071-DA control/status register (DCSR)

1 A000 0020 PCI bus error address register (PEAR)

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PCI Host Bridge 7–7