User guide

7.3.4 Interrupts
When the PCI host bridge has errors to report, it uses the int_hw0 signal to
interrupt the CPU. It does not distinguish between hard and soft errors when
asserting the interrupt signal.
The PCI host bridge does not provide an interval timer interrupt so this
functionality must be provided to the CPU by some other device in the system.
In addition, interrupts from other PCI devices or from a PCI interrupt controller
must be sent directly to the CPU without intervention.
The PCI host bridge participates in the interrupt acknowledge process. When the
CPU sends read block commands to the interrupt acknowledge address space, the
PCI host bridge performs an interrupt acknowledge transaction on the PCI bus.
The interrupt vector from the PCI bus is returned to the CPU through the system
bus by the PCI host bridge.
7.3.5 Exclusive Access
The PCI host bridge uses the lock_l signal to conform to the PCI Exclusive
Access protocol. When the PCI bus detects a latched transaction to main memory,
the PCI host bridge locks out all main memory accesses.
The PCI host bridge disconnects the transaction without completing any data
transfers. Until the lock is cleared, only the PCI bus master that sent the latched
transaction is allowed to complete transactions to main memory (see the PCI
Local Bus Specification).
In the system bus interface, the lock causes the system lock flag to be cleared by
using the ioclrlock command encoded on the iocmd<2:0>. The system lock flag
stays cleared until all latched transactions have been completed and the lock is
cleared.
7.3.6 Bus Parking
When no devices are requesting bus mastership, that is, the PCI host bridge is
not the target of any transaction, Digital recommends that the PCI host bridge
asserts its iogrant signal to gain ownership of the PCI local bus. This reduces
the latency for CPU-initiated transfers to the PCI bus when the bus is idle.
When the PCI host bridge owns the PCI bus, it drives ad<31:0>, cbe_l<3:0>,
and par signals. The PCI Local Bus Specification refers to this practice of giving
ownership of the PCI bus as bus parking.
The PCI host bridge also supports PCI bus parking during reset. If the iogrant
signal is asserted by the system arbiter (req_l is always tristated by the 21071-
DA chip during reset), the PCI host bridge drives ad<31:0>, cbe<3:0>, and (one
clock cycle later) par. When the iogrant signal is deasserted, the 21071-DA chip
tristates these signals.
7–6 PCI Host Bridge