User guide

7.2.3 Burst Length and Prefetching for PCI bus
On write transactions directed toward main memory, the PCI host bridge
supports a maximum burst length of 16 longwords. For the maximum burst, the
write transaction must start on an even cache-line boundary with PCI ad<5> =
0 and PCI ad<4:2> = 0. The transaction is terminated using a PCI disconnect
after the sixteenth longword has been received. In all other cases, the burst is
less than 16 longwords.
On DMA read transactions, the PCI host bridge supports a maximum burst
length of 16 longwords if DMA prefetching is enabled in the 21071-DA and the
requesting device uses a PCI read multiple command. If DMA prefetching is not
enabled and the requesting device does not use a PCI read multiple command,
the maximum burst length is eight longwords.
7.3 Features
7.3.1 Burst Order
In memory transactions, the master specifies the burst order. The PCI host
bridge stores the burst order in PCI address bits ad<1:0>. When the PCI host
bridge is a master of the PCI local bus, it always specifies a linear-incrementing
burst order ad<1:0> =0.
On DMA transactions, the PCI host bridge supports burst transfers only if a
linear-incrementing burst order is specified. If the master specifies a different
burst order, that is, ad<1:0> is nonzero, the PCI host bridge disconnects the
transaction after one data transfer.
7.3.2 Parity Support
According to the Local PCI Bus Specification, all PCI devices generate parity
across PCI data and address lines (ad<31:0>) and across command and byte
enables (cbe#<3:0>). The PCI host bridge complies with this specification and,
when it is master of the PCI bus, it also checks:
• The incoming parity on I/O read transactions
• Interrupt vector read transactions
• Configuration read transactions during data phases
On memory write transactions, when the PCI host bridge is a target, it checks
parity during the address phase and data phases.
7–4 PCI Host Bridge